1. Field
The present technology relates to three-dimensional memory devices, and methods for manufacturing such devices.
2. Description of Related Art
In the manufacturing of high density memory devices, the amount of data per unit area can be a critical factor. Thus, as the critical dimensions of the memory devices approach technology limits, techniques for stacking multiple levels of memory cells have been proposed in order to achieve greater storage density and lower costs per bit.
For example, a three-dimensional stacked memory device with anti-fuse diode memory cells is described in Johnson et al., “512-Mb PROM with a Three-Dimensional Array of Diode/Anti-fuse Memory Cells” IEEE J. of Solid-State Circuits, vol. 38, no. 11, November 2003. In the design described in Johnson et al., multiple layers of word lines and bit lines are provided, with memory elements at the cross-points. The memory elements comprise a p+ polysilicon anode connected to a word line, and an n-polysilicon cathode connected to a bit line, with the anode and cathode separated by anti-fuse material. Although the benefits of high density are achieved using the design described in Johnson et al., diodes having both the anode and cathode regions made of polycrystalline silicon may have unacceptably high off current. Diodes having both regions made of single crystal silicon may provide a suitably low off current, but processes for making such devices are complex.
A three-dimensional stacked memory device structure that provides vertical NAND cells in a charge trapping memory technology is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15. The structure described in Tanaka et al. includes a multi-gate field effect transistor structure having a vertical channel which operates like a NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a pillar of polycrystalline silicon arranged as the vertical channel for the multi-gate cell. However, it has been observed that grain boundaries and intragranular defects within channels of polycrystalline silicon can adversely affect transistor performance. For example, device characteristics such as threshold voltage, leakage current and tranconductance can be poor compared to devices having single crystal channels.
It is desirable to provide a structure for three-dimensional integrated circuit memory, including memory cells using single crystal semiconductor elements.